eCAD Bridge
Homechevron_right Calculatorschevron_right FpGenchevron_right Sym Craftchevron_right Articlechevron_right Postchevron_right Videoschevron_right Contactchevron_right
personProfile loginLogin
IEEE-315 SYNTHESIS ENGINE: ONLINE
| Part: STM32F401RCT6 (LQFP-64)
v2.4.1-r3
✓
Step 01

Load Pin Matrix

Matrix Ready

Parsed from spreadsheet with automated electrical pin-type categorization.

02
Step 02 • Active

Preview & Validate Symbol

Active Workbench

Validate IEEE-315 geometry, pin stubs, grid snaps, and pin 1 index positioning.

03
Step 03

Export ECAD Bundles

4 Formats Ready

Instant packaging for KiCad v7/v8, OrCAD OLB, Concept HDL, and Altium.

dataset

1. Pin Ingestion Matrix

UTF-8 / CRLF
upload_file

Drop spreadsheet or click to browse

Supports .xlsx, .csv, .tsv, .kicad_sym, IBIS (.ibs)

task_alt

STM32F401RCT6_pins.csv

Active pin model loaded

Ready
Split:
pin

Pin Mapping Registry

search
TOTAL 0 L 0 R 0 T 0 B 0
single-section part
# Name Side Type
edit_note

2. Symbol Attributes & Metadata

IPC-7351C
schema Schematic Symbol
STM32F401RCT6 (U1)
64 Pins Total Grid: 50.0 mil (1.27mm) check_circle DRC: 0 Violations (Pass)
100%
Origin: (0.0, 0.0) mil | Snap: 50.0 mil
Pin 1 Inspector (VBAT)
50 mil Snap PASS
Electrical Type: Power In (3.3V Backup)
Stub Coordinates: X: -100.0 mil | Y: +350.0 mil
Stub Orientation: Left-to-Right (Angle 0°)
Pin Length: 100.0 mil (2.54 mm standard)
Inversion Symbol: None (Active High)
Interactive Pin Probe HUD
FpGen ↗
LQFP-64
10x10mm 0.5P
bolt
Step 03 Complete All 4 Engines Synthesized

Export Symbol Library Artifacts

Directly importable files generated for major ECAD schematic capture suites.

OrCAD Capture

.OLB

Cadence OrCAD batch compiled library with pin sequencing & TCL scripts.

Individual Output Files
code build_lib.tcl
table_chart pins.csv
image symbol.svg
format_list_numbered partseq.csv
data_object part.json
OrCAD 17.2, 17.4 & 23.1 Ready

Concept HDL

Allegro HDL

Allegro Design Entry HDL package directory with Verilog/VHDL definitions.

Individual Output Files
inventory_2 chips.prt
style symbol.css
reorder pinlist.txt
terminal verilog.v / vhdl.vhd
tune part.prf
Cadence Design Systems HDL 16.6+

KiCad EDA

v7 / v8

Native S-expression syntax symbols, footprint mappings, and documentation index.

Individual Output Files
extension STM32F401RCT6.kicad_sym
description STM32F401RCT6.dcm
history_edu STM32F401RCT6.lib (Legacy)
KiCad v6, v7, and v8 Compatible

Altium Designer

.SchLib

DelphiScript batch importer, binary schematic library, and ASCII pin model.

Individual Output Files
terminal build_schlib.pas
table_rows altium_pins.csv
developer_board STM32F401RCT6.SchLib
Altium 20, 21, 22, 23 & 24 Verified
terminal KiCad v7 / v8 Setup
  1. Open KiCad Schematic Editor.
  2. Navigate to Preferences > Manage Symbol Libraries.
  3. In Global or Project tab, click the folder icon and select STM32F401RCT6.kicad_sym.
  4. Add part to canvas via hotkey A.
CLI Verification command: kicad-cli sym export-svg -o out.svg STM32F401RCT6.kicad_sym
developer_board Altium Designer
  1. Open Altium Designer.
  2. Open Panels > Components.
  3. Click the top hamburger menu > File-based Libraries Preferences.
  4. Click Install and choose STM32F401RCT6.SchLib.
DelphiScript Import Automation: RunScript("build_schlib.pas", "ImportSymbol")
integration_instructions OrCAD Capture .OLB
  1. Launch OrCAD Capture CIS.
  2. Select File > Open > Library.
  3. Select the compiled .OLB package file.
  4. Or source the generator script in the Command Shell:
Capture Tcl/Tk Shell command: source build_lib.tcl
memory Concept HDL
  1. Copy unpacked directory into your project's CAD library path.
  2. Confirm the presence of chips.prt and part.prf.
  3. Run Design Entry HDL > Tools > Update Parts Table.
  4. Place part in schematic via Global Catalog search.
Packaging verification batch: parttable -check chips.prt
verified All exports strictly adhere to IEEE Std 315-1975 & IEC 60617 graphical symbology standards.
Checksum SHA-256: 8f4e91...d2c0b4